5G 正在快速發(fā)展,并且正在推動(dòng)各種激動(dòng)人心的技術(shù)的發(fā)展 – 包括增強(qiáng)現(xiàn)實(shí)、人工智能、云計(jì)算和物聯(lián)網(wǎng)。所有這些數(shù)據(jù)都需要存儲(chǔ)在某個(gè)地方并以前所未有的速度進(jìn)行訪問,這意味著像 DDR5 這樣的技術(shù)從未如此重要。DDR5 改善了帶寬、密度和通道效率,但是更高的數(shù)據(jù)傳輸速率和更快的信號(hào)速度意味著復(fù)雜的設(shè)計(jì)將突破信號(hào)完整性的界限,并對(duì)合規(guī)性、調(diào)試和驗(yàn)證提出了更高的性能測(cè)量要求。
泰克 TekExpress DDR5 發(fā)射機(jī)解決方案是一種自動(dòng)化的系統(tǒng)級(jí)測(cè)試應(yīng)用,可讓您快速、有效和可靠地驗(yàn)證和調(diào)試 DDR5 設(shè)計(jì),以滿足 JEDEC 定義的 50 多種電氣和時(shí)序測(cè)量要求。
在存在符號(hào)間干擾 (ISI) 的情況下測(cè)試 DDR5 設(shè)計(jì)時(shí),最佳的 DDR3/4 調(diào)試工具仍顯不足。我們的 DDR5 系統(tǒng)級(jí)一致性軟件提供了多種自動(dòng)化工具來克服下一代 DDR 帶來的挑戰(zhàn),其中包括:
泰克的 LPDDR5 發(fā)射機(jī)解決方案將控制權(quán)歸還給用戶。用戶自定義采集模式可讓您通過自定義示波器設(shè)置(例如采樣率、記錄長(zhǎng)度、帶寬等)來運(yùn)行 LPDDR5 JEDEC 一致性測(cè)量。
讀/寫突發(fā)分離一直是存儲(chǔ)器驗(yàn)證工程師的主要問題。通常,在系統(tǒng)級(jí)別上,無法控制 DDR 總線上的數(shù)據(jù)流量。LPDDR5 發(fā)射機(jī)解決方案采用新的改進(jìn)突發(fā)分離算法,不僅可以同時(shí)進(jìn)行讀/寫突發(fā)檢測(cè),而且還可以縮短測(cè)試時(shí)間和提高準(zhǔn)確性。
在反嵌 LPDDR5 設(shè)計(jì)時(shí),驗(yàn)證 S 參數(shù)通常是主要的考慮因素。借助改進(jìn)的無源檢查、端口分配和繪圖功能,串行數(shù)據(jù)鏈路分析 (SDLA) 不僅增強(qiáng)了 S 參數(shù)文件的驗(yàn)證能力,而且還提高了靈活性,節(jié)省了時(shí)間并增加了對(duì)反嵌過程的信心。其他調(diào)試軟件工具需要您完成整個(gè)過程才能找到結(jié)果。泰克的 LPDDR5 發(fā)射機(jī)解決方案可幫助您在早期階段發(fā)現(xiàn)問題,從而提高調(diào)試效率并優(yōu)化設(shè)計(jì)。SDLA 功能也可用于 DFE 分析。
有關(guān)更多信息,請(qǐng)?jiān)诖瞬榭次覀兊?SDLA 應(yīng)用程序注釋。
The DDR (Dual Data Rate) is a dominant and fast-growing memory technology. It offers high data transfer rates required for virtually computing applications, from consumer products to the most powerful servers. The high speed of these signals requires high-performance measurement tools. The Tektronix TekExpress DDR Tx is an automated test application used to validate and debug the DDR5 designs of the DUT as per the JEDEC specifications. The solution enables you to achieve new levels of productivity, efficiency, and measurement reliability.
UDA: The TekExpress DDR Tx ‘DDR5’ Transmitter Solution puts control back where it should be, with the user. User defined acquisition mode allows you to run DDR5 JEDEC compliance measurements by customizing scope settings like sample rate, record length, bandwidth, and more
Tektronix provides the most comprehensive solution to serve the needs of the engineers designing DDR silicon for server, computer, graphics systems, mobile, embedded systems, and for those who are validating the physical-layer compliance of DDR Memory Compliance Test Specification.
The Tektronix option DDR5SYS (TekExpress DDR Tx) includes compliance and debug solution for the following:
The Tektronix option DDR5SYS is compatible with the following Tektronix oscilloscope models:
The above-mentioned Tektronix oscilloscopes are designed to meet the challenges of the next generation memory standards and provide the industry’s leading vertical noise performance with the highest number of effective bits (ENOB) and flattest frequency response for oscilloscopes in their class.
The Tektronix TekExpress DDR Tx solution reduces the effort and accelerates the compliance testing for DDR systems and devices with several unique and innovative capabilities.
The TekExpress DDR Tx application provides a simple, step-by-step, and easy-to-use interface to speed up the testing process. User can select the memory technology of interest in Device, Data Rate, Burst Detection Method, select the probing configuration used for Clock, and strobe in the Setup DUT panel, in the next step perform the test selection as per measurement group (Clock, Command Address, Data Strobe, and Data for both Read and Write traffic (or bursts)) and individual measurements within the group provide different methods of Burst detection.
The TekExpress DDR Tx application comes with a unique feature to select or deselect the signal. Once the signal is selected in the acquisition panel, the user can select the signal source connected to the oscilloscope.
Easily de-embed the interposer and the probe effects by applying suitable de-embed filters within the DDR5 standard.
The option DDR5SYS adds a long list of JEDEC specific measurements for DDR5 memory standards. The TekExpress DDR Tx application covers Electrical measurements, Timing measurements, and Eye Diagram measurements as per the JEDEC standards.
The TekExpress DDR Tx provides different ways to detect the burst cycles that are used to perform measurements:
The TekExpress DDR Tx test selection panel allows the user to select the various measurements supported by the application.
Supports 52 measurements of DDR5 System Transmitter Tests as per DDR5 JEDEC specification:
Ease of use measurement configuration to configure measurements by group instead of running through all the 50+ measurements.
The DDR5 application supports data rates from 3200 MT/s to 6400 MT/s. This increase in the data rate is realized without the need for differential signaling at the DQ pins i.e. the DQ bus is single-ended – same as DDR3/4. However, due to the many impedance mismatched points that exist along with the memory subsystem, ISI due to reflections are expected to increase. At data rates >= 4800 MT/s, the data eye at the DRAM ball is expected to be closed. A 4-tap DFE is implemented in the DDR5 DRAM Rx to help equalize the DQ signals and open the data eyes after the data is latched by the receiver.
The TekExpress DDR Tx application provides DDR DFE as a standalone software application in Tektronix’s performance scopes. It is used to perform 4 tap DFE operation on the DDR5 write burst signals coming from the DDR5 DUTs.
The measurement configurations and JEDEC pass/fail limits are automatically applied for the selected measurements based on the memory specification and the selected speed grade. The results report includes DDR measurements statistical data, measurement plots, and the screenshot of the waveforms with the cursors. Hyperlinks within the report allows you to navigate between the sections.
When test execution is complete, the application automatically opens the Results panel and displays the summary of test results.
The TekExpress DDR Tx application provides a comprehensive set of JEDEC timing and electrical measurements for the DDR5 standard. Also, it provides access to the DPOJET advanced Jitter and Timing analysis engine that allows flexibility to reconfigure the existing measurements or to perform new measurements that are not defined by the JEDEC specification using new user-specified test limits. Additionally, it features logging, filters, histograms, and time trends that are available in DPOJET. The user can also switch between debug mode and the compliance mode.
The Tektronix Pinpoint??trigger system provides the most comprehensive high-performance trigger system in the industry. The Pinpoint trigger system encompasses threshold and timing related triggers, Dual A and B Event Triggering, Logic Qualification, Window Triggering, and Reset Triggering.
The Advanced Search and Mark feature in the Tektronix MSO/DPO5000, DPO7000, and MSO/DPO70000 Series oscilloscopes find unique events in the waveforms. It scans acquired waveform data for multiple occurrences of an event and marks each occurrence.
The Search and Mark feature has a close relationship with the Pinpoint trigger system since they both can be used to discriminate signal characteristics. Search and Mark includes signal-shape discrimination features of the Pinpoint trigger system and extends them across live channels, stored data, and math waveforms.
The Visual Trigger makes the identification of the desired waveform events quick and easy by scanning all the acquired analog waveforms and comparing them with the geometric shapes on the display. By discarding the acquired waveforms which do not meet the graphical definition, Visual Triggering extends the oscilloscope’s trigger capabilities beyond the traditional hardware trigger system.